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|
Pdf Specs |
Exp |
Trainers |
Model |
2 |
Universal Logic gates |
DLG19 |
|
Boolean Algebra
Trainer |
DLG18 |
|
De-Morgan's Theorems
verification |
DLG17 |
|
4 Bit Half Adder and
Full Adder |
DMTH01 |
|
4 Bit Half Subtractor
and Full Subtractor |
DMTH03 |
|
4 Bit BCD Adder |
DMTH02F |
|
4 Bit Magnitude
Comparator |
DMTH07B |
|
2 Bit Binary
Multiplier |
DMTH08 |
|
Multiplexer /
Demultiplexer Trainer |
DENC06 |
|
Encoder / Decoder
Trainer |
DENC12 |
|
Parity Generator
|
DG01 |
3 |
Flip Flops Trainer -
R-S, J-K, T & D |
DFF100 |
|
4 Bit Binary Counter
- Asynchronous |
DCO08 |
|
4 Bit Decade Counter
using IC 7490 - Synchronous |
DCO02 |
|
4 Bit Up- Down
counter - Synchronous |
DCO09 |
|
4 Bit Modulo - N
Counter (N= 2to 9) using IC 74176- Synchronous |
DCO03 |
|
4 Bit Programmable (Presettable)
Counter - Synchronous |
DCO04 |
|
Shift registers (SISO,
SIPO, PISO, PIPO - All separate) Trainer |
DSR01-04 |
|
Ring Counter using
Shift Registers - Synchronous |
DCO12 |
|
Johnson Counter
Trainer |
DCO13 |
4 |
Random Access Memory
(RAM) static - 1K x 1 Bit |
DM01 |
|
EPROM Trainer - 2K x
8 Bit - using IC 2716 |
DM04 |
5 |
Xilinx XC 9500 CPLD
Series Trainer |
XC9500 |
|
Xilinx XC 4000 FGPA
Series Trainer |
XC4000 |
|
VHDL implementation
of basic combinational and sequential Circuits |
VDHL100SIM |
|
Programmable Logic
Devices: PLA |
PLA100 |
|
Programmable Logic
Devices: PAL |
PAL100 |
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