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E&TC - Semester - 7 - VLSI Design Lab - 404187

		Pdf Specs	All Specs Zip
		Model
I	VLSI Trainer	VLSI100P
	To write VHDL code, simulate with test bench, synthesis, implement on PLD.
1	4 bit ALU for add, subtract, AND, NAND, XOR, XNOR, OR, & ALU pass.
2	Universal shift register with mode selection input for SISO, SIPO, PISO, & PIPO modes.
3	FIFO memory.
4	LCD interface.
5	Keypad interface.
II	VLSI Trainer	VLSI101P
	To prepare CMOS layout in selected technology, simulate with and without  capacitive load, comment on rise, and fall times.
1	Inverter, NAND, NOR gates, Half Adder
2	2:1 Multiplexer using logic gates and transmission gates.
3	Single bit SRAM cell.
4	D flip-flop.