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ELEX - Semester - 7 - VLSI Design Lab - 404206

		Pdf Specs
Exp	VLSI Trainer	Model
(A)	To write VHDL code and test bench, synthesis, simulate and	VLSI102P
	down load in to PLD, for the following
1	To design of ALU to Perform – ADD, SUB, AND, OR, 1‟s compliment,
	2‟s Compliment, Multiplication and Division
2	To design of Sequence Detector
	(Finite State Machine- Mealy and Moore Machines).
3	To generate ramp/square waveform using DAC
4	To measure the period of a signal.
5	To design lift/traffic light controller
6	To design of 4-bit binary, BCD counters (synchronous/ asynchronous reset)
	VLSI Trainer
(B)	To prepare CMOS layout in selected technology, simulate with and	VLSI103P
	without capacitive load, comment on rise and fall times
1	CMOS Inverter and also observe VTC and calculate switching threshold
2	CMOS 3-input NAND, 3-input NOR.
3	2:1 MUX by conventional method & by using Transmission gates. Compare them.
4	CMOS Combinational logic for minimum 5 variables.
5	D/ T Flip flop.
6	Single bit SRAM cell.